The present invention relates to the packaging of chips and, more particularly, relates to an improved metallurgical structure for joining a chip to a substrate and for making engineering changes.
On the top surface of a semiconductor chip, there is an arrangement of chip pads, each with a solder ball (hereafter referred to as C-4 solder ball pads or just C-4s) which are adapted to provide connection between the chips and a ceramic substrate by means of bonding of the solder balls which are heated to a temperature above the melting temperature of the solder balls thereby permitting solder bonding of the solder balls to the pads carried on the upper surface of the substrate. Connected between the solder pad areas and other sites on or in the substrate are so-called fan-out lines which extend along the top surface of the substrate beneath a layer of insulation. At certain locations on the surface of the substrate, it is necessary to make pads available for engineering change wiring to be connected to the fan-out metallurgy. The engineering change wiring, however, is usually connected to the pads by the process of wire bonding, either by ultrasonic vibration or by thermo-compression techniques, although solder bonding has also been proposed. The metallurgical requirements for solder bonding as contrasted with the requirements for wire bonding techniques differ.
In Bhattacharya et al. U.S. Pat. No. 4,463,059, the disclosure of which is incorporated by reference herein, the metallurgical requirements for solder bonding and wire bonding are discussed in the context of the top surface metallurgy of a ceramic substrate. Several metallurgical structures are proposed. For solder bonding, one proposed structure consists of fan-out lines of chromium and gold, then a barrier layer of cobalt or chromium over the gold followed by a top layer of nickel or copper. For wire bonding, the nickel or copper top layer is eliminated. In other structures, Bhattacharya et al. suggests the use of gold where solder bonding is to occur.
Merrin et al. U.S. Pat. Re. 27,934 discusses the requirements of ball limiting metallurgy, i.e. the pads on the bottom of the chip which serve to limit the flow of the solder balls upon heating. The particular ball limiting metallurgy proposed by Merrin et al. comprises subsequent layers of chromium, copper and then gold. Similarly, Research Disclosure 267026 discloses a ball limiting metallurgy comprising subsequent layers of chromium or titanium, nickel or copper followed by a top layer of gold. The disclosures of both of these references are incorporated by reference herein.
Arnold U.S. Pat. Nos. 3,982,908 and 4,065,588, the disclosures of which are incorporated by reference herein, both disclose metallurgical structures for silicon devices comprising subsequent layers of nickel, gold and cobalt or gold and cobalt, respectively.
The present day top surface metallurgy for ceramic substrates may comprise a multilayered metallurgical structure of chromium or titanium, copper and then gold or, alternatively, molybdenum, nickel and then gold. The currently favored ball limiting metallurgy comprises chromium, copper and gold. Both the top surface metallurgy (hereinafter TSM) and the ball limiting metallurgy (hereinafter BLM) undergo many solder reflow operations during the process of joining the chips to the ceramic substrate. The gold in the TSM and BLM quickly dissolves in the solder, leaving the underlying copper (or nickel) to react with the solder which is usually of a lead/tin composition. The solder and the underlying copper (or nickel) have been chosen because they form a good solder joint.
The reaction of the copper and the solder, however, causes the formation of copper/tin intermetallics. Ordinarily, this would not be a problem but due to the multiple solder reflows necessary to join the chips to the ceramic substrate, the copper/tin intermetallics, eventually build up to the point where they spall off the underlying metallization, resulting in the loss of BLM conduction as well as the loss of a reaction barrier between the solder and the underlying chip metallization. Further, the spalling of these intermetallics can lead to early failure of the solder joint, an undesirable circumstance.
It would thus be an important step to be able to eliminate copper/tin intermetallics and their accompanying problems.
Accordingly, it is an object of the invention to have an improved joint between electronic components which is not as susceptible to excessive formation of intermetallics and their accompanying problems.
It is another object of the invention to have an improved joint between electronic components comprising a metallurgical structure which has a reduced rate of reaction with solder.
It is yet another object of the invention to have an improved joint between electronic components after multiple solder reflows.
These and other objects of the invention will become more apparent after referring to the following description considered in conjunction with the accompanying drawings.